1. Field of the Invention
The present invention relates generally to voltage generation circuits, and more specifically, to a voltage generation circuit capable of supplying a stable power supply voltage to a load operating in response to a timing signal applied from an external element, such as a sense amplifier in a semiconductor memory device.
2. Description of the Background Art
As the miniaturization has proceeded to meet the demand for semiconductor memory devices with increased capacity, the breakdown voltage of the internal circuitry of semiconductor devices has been lowered. There has been a demand in the market for a semiconductor memory device with power consumption reduced by lowering the operation voltage of the semiconductor memory device for example in connection with its application to portable equipment. To cope with this situation, the semiconductor memory device includes an internal power supply circuit and uses an appropriate internal power supply voltage obtained by lowering an external power supply voltage VCE of 5 V or 3.3 V for example to 2.5 V or 2.0 V.
Each of sense amplifier circuits included in a semiconductor memory device amplifies a very small voltage difference between bit lines to which memory cell data is read out, and high speed performance is necessary for the amplifying operation. The sense amplifier circuits generally operate by internal power supply voltage Vcc from such a power supply circuit provided inside.
In a semiconductor memory device, data in all the memory cells connected to the identical word line must be read out onto a bit line pair for each row selecting operation, a large number of sense amplifier circuits operate at the same time. A large amount of charges is supplied for a short period of time accordingly, when the sense amplifier circuits operate, and the voltage of a Vcc line supplying a power supply voltage to the sense amplifier circuits is temporarily lowered. This prevents a very small voltage difference generated between the lines of a bit line pair from being amplified fast, which results in a reduced operation speed.
There is a demand for an internal power supply voltage generation circuit which can supply stable internal power supply voltage Vcc to a load such as a sense amplifier which abruptly consumes a large amount of charges.
FIG. 19 is a schematic block diagram of a conventional internal power supply voltage generation circuit 500 used for this purpose by way of illustration.
Referring to FIG. 19, internal power supply voltage generation circuit 500 supplies internal power supply voltage Vcc to a load (sense amplifier) 517 by an internal power supply line 515.
A control target voltage for internal power supply voltage Vcc is provided by a prescribed DC voltage Vref1. Internal power supply generation circuit 500 includes a voltage comparing circuit 501 to generate an output voltage Vo corresponding to the difference between internal power supply voltage Vcc and Vref1 (Vcc-Vref1) and a current supply transistor 505 which receives output voltage Vo at its gate to connect an external power supply line 511 supplying external power supply voltage VCE and internal power supply line 515.
A current mirror circuit amplifier is typically used for voltage comparing circuit 501. External power supply voltage VCE and a ground voltage Vss are applied through a power supply switch 502.
Internal power supply voltage generation circuit 500 turns on current supply transistor 505 according to the output voltage Vo of voltage comparing circuit 501 when internal power supply voltage Vcc is lower than Vref1 and keeps internal power supply voltage Vcc at a constant level by supplying current Ic from external power supply line 511 to internal power supply line 515.
In internal power supply voltage generation circuit 500, however, during the actual period since internal power supply voltage Vcc is lowered until current supply transistor 505 is turned on, prescribed control delay corresponding to the response time of voltage comparing circuit 501 is present. This control delay is disadvantageous for example when a plurality of loads such as sense amplifiers operate in parallel in a short period of time in a semiconductor memory device.
FIG. 20 is a schematic diagram for use in illustration of a problem associated with internal power supply voltage generation circuit 500 when large current is consumed by a load in a short period of time.
Referring to FIG. 20, Vcc" is a waveform representing the fluctuation of internal power supply voltage Vcc when no feedback control is performed.
At time t1, the load is activated and current is consumed, which temporarily lowers internal power supply voltage Vcc.
In this case, if internal power supply voltage generation circuit 500 is operated, and a time lag .DELTA.t exists until the lowering of internal power supply voltage Vcc is actually reflected on output Vo to voltage comparing circuit 501, current supply transistor 505 will not conduct during the period of .DELTA.t, and therefore Vcc decreases similarly to Vcc'.
Then, at time t2 after time lag .DELTA.t corresponding to the response time of voltage comparing circuit 501 since time t1, comparison output voltage Vo starts to be lowered, which gradually turns on current supply transistor 505, and power supply current Ic is allowed to flow from external power supply line 511 to internal power supply line 515. This power supply current Ic allows internal power supply voltage Vcc to regain the level of control target voltage Vref1.
After internal power supply voltage Vcc returns to the level of reference voltage Vref1, similar response time is present in voltage comparing circuit 501, therefore current supply transistor 505 will not be turned off soon, and internal power supply voltage Vcc is raised to a level higher than Vref1. If the response time .DELTA.t of voltage comparing circuit 501 is large, internal power supply voltage Vcc could be sometimes raised to too high a level in comparison with Vref1 and in such a case, a circuit to lower internal power supply voltage Vcc should be separately provided.
Thus, if the load abruptly consumes large current, internal power supply voltage Vcc cannot be stably supplied simply by performing feedback control of internal power supply voltage Vcc by a voltage comparing circuit such as current mirror amplifier which must take the response time into consideration.
Therefore, an internal power supply voltage generation circuit to stably supply an operation power supply voltage to a load whose operation timing is previously known is disclosed by Japanese Patent Laying-Open No. 10-27026.
FIG. 21 is a circuit diagram showing the general structure of an internal power supply voltage generation circuit 510 disclosed by this document.
Referring to FIG. 21, internal power supply voltage generation circuit 510 supplies operation voltage VCI to a load 512.
Operation voltage VCI is provided to a voltage comparing circuit 511 as a feedback voltage signal DCI through a transistor Q2. Voltage comparing circuit 511 outputs an output voltage corresponding to the voltage difference between feedback voltage signal DCI and a reference voltage Vref2 to a node S1. A current supply transistor Q1 supplies current from external power supply voltage VCE to load 512 when operation voltage VCI is lowered in response to the voltage at node S1 and functions to keep operation voltage VCI constant.
In internal power supply voltage generation circuit 510, reference voltage Vref2 is generated by a reference voltage generation circuit 513. Reference voltage generation circuit 513 includes a current source I2 and resistors R23 and R24 connected in series between the external power supply and the ground line. To both ends of resistor R23, the source and drain of a transistor Q8 are connected. A control signal S8 is applied to the gate of transistor Q8 and resistor R23 is short-circuited while transistor Q8 is on by control signal S8. A node N6 is connected between low current source 12 and resistor R23. The voltage generated at node N6 is applied to voltage comparing circuit 511 as reference voltage Vref2.
With reference voltage generation circuit 513 having this configuration, reference voltage Vref2 can be changed into pulse-wise according to control signal S8.
More specifically, if the operation timing of load 512 is previously known, control signal S8 can be controlled prior to an activation timing of load 512 to set reference voltage Vref2 to a value higher than normal, so that current supply transistor Q1 can be turned on in coincidence with the operation timing of load 512.
Thus, even using voltage comparing circuit 511 involving the response delay, effective control can be performed to a load which consumes large current in a short period of time if the operation timing of the circuit is previously known, and by controlling operation voltage VCI to be stable, the problem described in conjunction with FIG. 20 is addressed.
Reference voltage generation circuit 513 included in internal power supply voltage generation circuit 510 adjusts the reference voltage within the range from the ground voltage to external power supply voltage VCE by the presence/absence of a short circuit of a resistor.
However, in reference voltage generation circuit 513 having this configuration, there is current allowed to flow through the path of external power supply VCE--current source I2--resistor R23--resistor R24--ground line Vss, current is wasted. A relatively large number of circuit elements including resistors and transistors are necessary, which is disadvantageous in terms of layout. These problems could pose further potential shortcomings since semiconductor memory devices will be probably increased in scale in the future.
In addition, in reference voltage generation circuit 513, when the voltage difference between the reference value of operation voltage VCI and external power supply voltage VCE is small, the pulse amplitude which can be generated by control signal S8 could be small, which could impair improvement in responsiveness. If feedback voltage signal DCI is generated through a voltage dividing circuit to cope with this end, the described disadvantage associated with the layout is further amplified.
In view of the future development of semiconductor memory devices, the operation voltage will be necessarily further lowered and external power supply voltage VCE and the operation voltage VCI of the internal circuit will be further lowered. Then, the above described problem will be more serious in this context.